Die-level test

Die-level test is characterization performed on individual photonic dies after the wafer has been singulated (diced into separate chips) but before each die is permanently packaged. It complements wafer-level test, which catches most defects pre-dicing; die-level test handles the parameters that intrinsically require a singulated die.

Why die-level test is needed. Three categories of measurements cannot be performed at wafer level:

1. Edge-coupling measurements — require a polished die facet that does not exist before dicing
2. High-power destructive screens — risk damaging neighbor dies on the wafer
3. Specialized environmental tests — cryogenic operation, high vibration, or hermetic-sealed measurement chambers

Typical die-level setup:

Component	Function
Submount with vacuum chuck pocket sized for one die	Holds the chip at known position with TEC for thermal control
6-axis precision stage with lensed-fiber input	Edge coupler input alignment
6-axis precision stage with lensed-fiber output	Throughput measurement at output edge
Tunable laser + photodetector + lock-in / OSA	Optical characterization at full system sensitivity
Wafer probe-station style electrical probes	DC bias and RF drive when needed

Throughput. Per-die alignment takes 30 seconds to 5 minutes; full die-level characterization (sweep all input fibers, output fibers, electrical bias points) ranges from 1 minute to several hours depending on the device complexity. This is the dominant cost driver in InP laser foundry test, and it is one of the reasons silicon photonics emphasizes grating coupler-based wafer-level testing aggressively.

What die-level test catches that wafer-level misses:

Parameter	Why wafer-level cannot measure
Edge coupler loss	Polished facet needed
Mirror reflectivity (laser facet)	Polished facet needed
Full LIV (high current)	Risk of damaging adjacent dies
Coupling tolerance	Requires real alignment of input fiber
Polarization-resolved measurements	Edge access to TE/TM modes
Spectral output ($M^2$, RIN, linewidth)	Often requires post-coupling free-space optics
Initial burn-in	Stress conditions risk adjacent die damage

Selective die-level test. For high-volume manufacturing, the test plan is designed so that wafer-level test catches enough failures to make die-level test economic: only dies passing wafer-level test go to die-level test, dropping the population by 5–50%. Within die-level, parametric sampling (10–100% of dies) and screening (every die) is balanced against per-die cost.

Yield cascade example. A mature silicon photonic process:

• Wafer-level test yield: 90% (90% of dies pass)
• Of those, die-level edge-coupler test yield: 95% (95% of survivors)
• Burn-in pass rate: 99%

Combined yield from epi to packaged: $0.90 \times 0.95 \times 0.99 = 0.85$, or 85%.

For a new process or aggressive design:

• Wafer-level: 50%
• Die-level: 80%
• Burn-in: 90%
• Combined: 36%

The difference (85% vs 36%) directly drives unit cost.

Die-level burn-in. Some products combine die-level testing with burn-in: a stress soak at die level eliminates infant-mortality failures before more expensive packaging. This is standard practice for telecom-qualified InP laser products. Less common in silicon photonics, which generally relies on wafer-level screening and downstream qualification.

The transition between wafer-level and die-level test is one of the major workflow decisions in any photonic foundry — pushing more parameters to wafer-level reduces cost dramatically, but only some parameters are accessible without dicing.