Wafer-level test
Electrical and optical characterization of photonic or optoelectronic devices while they are still on the un-diced wafer, before any singulation or packaging. The dominant characterization mode in modern silicon photonic foundries.
Wafer-level test (sometimes called "wafer probe" or "wafer screening") is the practice of characterizing individual devices on a wafer before the wafer is diced into separate chips. Devices that fail the wafer-level screen are marked as "bad" and discarded after dicing; only devices that passed wafer-level test proceed to packaging.
Why wafer-level test is cheap. Packaging is the single most expensive operation in optoelectronic manufacturing — pigtailing a telecom laser module costs \100 – $500$ per unit. Discovering a failing device after packaging means the entire packaging cost is wasted. Wafer-level test detects most failures before any packaging cost is incurred, dropping the cost penalty per failure by 1–2 orders of magnitude.
Standard wafer-level test setup:
| Component | Function |
|---|---|
| Vacuum chuck stage with X/Y/θ stepping (sub-μm precision) | Position each die under the optical and electrical probes |
| Probe card with multiple electrical contacts | Apply bias, measure current/voltage, drive heaters |
| Optical input/output through grating couplers on the die | Fiber-coupled optical probes; vertical alignment to the chip surface |
| Tunable laser source + power meter | Optical characterization (transmission, loss, FSR) |
| Test execution system | Automates per-die measurements; logs results to wafer map |
Why grating couplers dominate wafer-level test. Edge couplers require polished facets, which means dicing the wafer — defeating the purpose of pre-dicing test. Grating couplers couple from the surface of the die at any position on the wafer, requiring only that a fiber tip be vertically aligned to the grating area. Modern silicon photonic foundry process design kits (AIM Photonics, IMEC iSiPP50G, GlobalFoundries 9WG) include grating couplers at standardized positions for automated wafer test.
Throughput. A typical silicon photonic wafer-level test station tests device every 5–30 seconds depending on test complexity. A full 200 mm wafer holds 100 – 500 reticles, each with 10 – 100 individual devices, giving total per-wafer test time of 5 minutes to several hours.
What is tested at wafer level for silicon photonics:
- Grating coupler loss — verifies optical I/O works at all
- Insertion loss of passive structures (waveguide spirals, MMIs, directional couplers)
- Resonator FSR and Q — verifies microring designs
- Modulator and bandwidth (RF probes required)
- Photodetector dark current and responsivity
- Heater resistance — verifies thermal tuners
- DC continuity — verifies no shorts or opens in metal stack
What requires post-dicing (die-level) test:
- Edge coupler loss — needs polished facet
- Final yield against system-level specs — combines device-level results
- High-temperature reliability — wafer chuck is typically room-temperature
- High-power damage threshold — risk of damaging neighboring devices on wafer
Yield mapping. Wafer-level test results are logged with die coordinates, producing a 2D wafer map showing pass/fail and parameter distributions across the wafer. Spatial patterns (edge ring failures, center vs edge gradients, defective reticles) often indicate specific process problems and feed back into process control. For mature silicon photonic processes, wafer-level pass rates of 80–95% are typical; for advanced research processes, 30–60% is more common.
Wafer-level test is the single largest factor enabling silicon photonics' cost-scaling story versus traditional III–V photonics. The fact that an InP wafer requires per-die cleaving and active alignment to even characterize its lasers, while a silicon photonic wafer can be tested at scale on a wafer chuck, is what makes large-volume silicon photonic transceiver manufacturing economically viable.
References: Chrostowski & Hochberg, Silicon Photonics Design (2015), Ch. 9 on wafer-scale testing; AIM Photonics PDK Test Methodology Guide.